Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

ABSTRACT

Apparatus and methods for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the design and testing ofintegrated circuit devices. Specifically, the present invention relatesto the electrical characterization of integrated circuit device packagesat high operating frequencies and, in particular, to apparatus andmethods for measuring parasitic capacitance and inductance of one ormore I/O leads of an integrated circuit device package using a networkanalyzer.

2. State of the Art

Designers of integrated circuit devices are facing increasinglydifficult challenges as a result of the current trend toward integratedcircuit devices exhibiting small overall package dimensions and having alarge number of leads, yet being capable of operating at highfrequencies. Such an integrated circuit device may include a complexarray of closely spaced electrical leads adapted for establishingelectrical communication with a semiconductor die, each lead having oneend electrically connected to the semiconductor die and an opposing endadapted for electrical connection to an external device, such as aprinted circuit board. Presently, a wide variety of integrated circuitpackage types and configurations are commercially available, including,for example, Ball Grid Array (BGA) packages, Thin Small Outline Packages(TSOPs), as well as other package types. It is a continuing goal ofintegrated circuit package designers to adapt these packageconfigurations to fit within ever-decreasing volumes, to include a largenumber of electrical leads, and to operate at high frequencies in orderto meet the demand for such devices.

An exemplary embodiment of a conventional BGA package is shown in FIGS.1 and 2. The conventional BGA package 100 may be a memory device, suchas a DRAM chip, a processor, or any other integrated circuit deviceknown in the art. The conventional BGA package 100 includes asemiconductor die 110 secured to a die-attach pad 112 formed on an uppersurface 106 of a substrate 105, which may also be termed an interposer.The BGA package 100 also includes a plurality of electrical leads 130adapted to provide electrical communication between the semiconductordie 110 and one or more external devices (not shown). The semiconductordie 110 and at least a portion of each electrical lead 130 may beencased by an encapsulant material 120 or, alternatively, theconventional BGA package 100 may have no encapsulant material, dependingupon the particular package construction and intended use.

Each of the electrical leads 130 includes an external ball lead 132configured for electrical connection to an external device. The balllead 132 may be secured to a conductive pad 133 formed on a lowersurface 107 of the substrate 105. Each electrical lead 130 furthercomprises a conductive via 134 extending from the conductive pad 133 andthrough the substrate 105 to a conductive trace 136. The conductivetrace 136 is formed on the upper surface 106 of the substrate 105 andprovides an electrical path from the conductive via 134 to a bond end137 located proximate the semiconductor die 110. A bond wire 138attached to the bond end 137 of the conductive trace 136 and extendingto the semiconductor die 110, where the bond wire 138 is attached to abond pad thereon, electrically connects the electrical lead 130 to thesemiconductor die 110. At least the bond wire 138 and conductive trace136 of each electrical lead 130 may be encased by the encapsulantmaterial 120.

The conventional BGA package 100 may include a plurality of the ballleads 132 arranged, for example, in an array or arrays of mutuallyadjacent rows and columns. Referring to FIG. 1, the ball leads 132 maybe arranged in two arrays 150, 160, each array 150, 160 disposed betweenan edge of the semiconductor die 110 and a peripheral edge of thesubstrate 105. Each array 150, 160 comprises three columns 151, 152,153, 161, 162, 163, respectively, of ball leads 132. The arrangement ofball leads 132 is typically referred to as the “pin-out” or the“footprint” of the BGA package 100. The pin-out of the BGA package 100may, by way of example, comprise outer and inner columns 151, 161, 153,163 of ball leads 132 adapted to provide input and output of electricalsignals to and from the semiconductor die 110, such leads being referredto herein as “I/O leads.” The pin-out may further comprise centercolumns 152, 162 of ball leads 132 adapted to provide a power signal tothe semiconductor die 110 (a “V_(CC) lead”), to provide a groundpotential for the semiconductor die 110 (a “V_(SS) lead”), or to providea reference voltage to the semiconductor die 110 (a “V_(REF) lead”).However, those of ordinary skill in the art will understand that theparticular pin-out of an integrated circuit device may vary dependingupon the application and that the pin-out may be of any suitableconfiguration.

An exemplary embodiment of a conventional TSOP is shown in FIGS. 3 and4. The conventional TSOP 200 may be a memory device, such as a DRAMchip, a processor, or any other integrated circuit device known in theart. The conventional TSOP 200 includes a semiconductor die 210 securedto a die-attach pad 212. The TSOP 200 further includes a plurality ofelectrical leads 230 adapted to provide electrical communication betweenthe semiconductor die 210 and one or more external devices (not shown).The semiconductor die 210 and at least a portion of each electrical lead230 are encased by an encapsulant material 220.

Each of the electrical leads 230 includes an external portion 232configured for electrical connection to an external device. Eachelectrical lead 230 also includes an internal portion 234 extending fromthe external portion 232 to a bond end 235 located proximate thesemiconductor die 210. A transversely extending bus bar or bars 239 mayextend between two or more electrical leads 230. A bond wire 238electrically connects the bond end 235 of the internal portion 234 to abond pad on the semiconductor die 210 to establish electricalcommunication therebetween. Bond wires 238 may also extend between thetransverse bus bar or bars 239 and one or more bond pads on thesemiconductor die 210. At least the internal portion 234 and bond wire238 of each electrical lead 230 are encased by the encapsulant material220.

The external portion 232 and internal portion 234 of each electricallead 230 typically comprise a single piece of material commonly referredto as a lead finger. Further, the lead fingers (external and internalportions 232, 234), bus bar or bars 239, and die-attach pad 212typically comprise a structure usually referred to as a lead frame.Integrated circuit packages utilizing lead frame construction are wellknown in the art. It will be appreciated by those of ordinary skill inthe art that the conventional TSOP 200 may include a lead frame of anyconfiguration known in the art and, further, that the internal portion234 may extend over and directly attach to the semiconductor die 210,such a lead frame being commonly referred to as a Leads-Over-Chip (LOC)configuration.

The external portions 232 of the electrical leads 230 extend from one ormore edges of the TSOP 200 and are arranged in a row therealong. Forexample, as shown in FIG. 3, the TSOP 200 may include a row 250 ofelectrical leads 230 extending from an edge of the TSOP 200 and anotherrow 260 of electrical leads 230 extending from an opposing edge of theTSOP 200. The arrangement of the external portions 232 of the electricalleads 230 comprises the pin-out or footprint of the TSOP 200. Anelectrical lead 230 may be an I/O lead, a V_(CC) lead, a V_(SS) lead, ora V_(REF) lead, as noted above, and the particular configuration of thepin-out will vary depending upon the application.

For both the conventional BGA package 100 and the conventional TSOP 200,as well as for other conventional integrated circuit package types, thespacing between the electrical leads 130, 230—especially betweenadjacent conductive traces 136 and between adjacent internal portions234 thereof, respectively—is becoming increasingly smaller toaccommodate smaller overall package sizes and greater numbers ofelectrical leads 130, 230, as was suggested above. This close spacingbetween adjacent electrical leads 130, 230 in the conventional BGA andTSOP packages 100, 200, respectively, in conjunction with increasinglyhigher operating frequencies for newer integrated circuit devices, maylead to mutual coupling between adjacent electrical leads 130, 230,which may compromise signal integrity during operation of the integratedcircuit package.

Mutual coupling between adjacent electrical leads of an integratedcircuit device, especially at high frequencies, presents a difficultproblem for integrated circuit package designers. The mutual couplingbetween adjacent electrical leads of an integrated circuit package, aswell as between an electrical lead and other components of theintegrated circuit package, may include mutual capacitance and mutualinductance, both of which are frequency dependent. Thus, as newerintegrated circuit packages are being designed to operate in relativelyhigher frequency ranges—e.g., in the range of 100 MHz to 400 MHz andhigher—the deleterious effects of mutual coupling on signal integritybecome increasingly significant, and package designers must have toolsavailable to quantify such effects. Mutual capacitances and mutualinductances within an integrated circuit package are commonly referredto as parasitic capacitance and parasitic inductance, or simplyparasitics.

Shown in FIG. 5 is an electrical model of two adjacent electrical leads130 a, 130 b in the conventional BGA package 100. The electrical lead130 a includes a resistance 801 a, an inductance 802 a, and acapacitance 803 a. Similarly, the electrical lead 130 b includes aresistance 801 b, an inductance 802 b, and a capacitance 803 b. Theelectrical model depicted in FIG. 5 is commonly referred to as a“lumped” model.

Referring to FIG. 5, the resistance 801 a comprises the individualresistances of the bond wire 138, the conductive trace 136, theconductive via 134, the conductive pad 133, and the ball lead 132 ofelectrical lead 130 a. The inductance 802 a comprises the individualinductances of the bond wire 138, the conductive trace 136, theconductive via 134, the conductive pad 133, and the ball lead 132 ofelectrical lead 130 a, and further including mutual inductancesgenerated between the electrical lead 130 a and the adjacent electricallead 130 b, as well as between the electrical lead 130 a and othercomponents of the BGA package 100. The capacitance 803 a comprises theindividual capacitances of the bond wire 138, the conductive trace 136,the conductive via 134, the conductive pad 133, and the ball lead 132 ofelectrical lead 130 a, and further including mutual capacitancesgenerated between the electrical lead 130 a and the adjacent electricallead 130 b, as well as between the electrical lead 130 a and othercomponents of the BGA package 100. The mutual inductances and mutualcapacitances are, at least in part, dependent upon the configuration of,and the distance between, the adjacent electrical leads 130 a, 130 b andupon the magnitude and frequency of the electrical signals propagatingthrough each of the adjacent electrical leads 130 a, 130 b, as well asthrough other surrounding electrical leads 130 and other components ofthe BGA package 100.

Similarly, the resistance 801 b comprises the individual resistances ofthe bond wire 138, the conductive trace 136, the conductive via 134, theconductive pad 133, and the ball lead 132 of the electrical lead 130 b.The inductance 802 b comprises the individual inductances of the bondwire 138, the conductive trace 136, the conductive via 134, theconductive pad 133, and the ball lead 132 of electrical lead 130 b, andfurther including mutual inductances generated between the electricallead 130 b and the adjacent electrical lead 130 a, as well as betweenthe electrical lead 130 b and other components of the BGA package 100.The capacitance 803 b comprises the individual capacitances of the bondwire 138, the conductive trace 136, the conductive via 134, theconductive pad 133, and the ball lead 132 of electrical lead 130 b, andfurther including mutual capacitances generated between the electricallead 130 b and the adjacent electrical lead 130 a, as well as betweenthe electrical lead 130 b and other components of the BGA package 100.Again, the mutual inductances and mutual capacitances are, at least inpart, dependent upon the configuration of, and the distance between, theadjacent electrical leads 130 b, 130 a and upon the magnitude andfrequency of the electrical signals propagating through each of theadjacent electrical leads 130 b, 130 a, as well as through othersurrounding electrical leads 130 and other components of the BGA package100.

Shown in FIG. 6 is an electrical model of two adjacent electrical leads230 a, 230 b in the conventional TSOP 200. The electrical lead 230 aincludes a resistance 901 a, an inductance 902 a, and a capacitance 903a. Similarly, the electrical lead 230 b includes a resistance 901 b, aninductance 902 b, and a capacitance 903 b. The electrical model depictedin FIG. 6 is commonly referred to as a “lumped” model, as noted above.

Referring to FIG. 6, the resistance 901 a comprises the individualresistances of the bond wire 238, the internal portion 234, and theexternal portion 232 of electrical lead 230 a. The inductance 902 acomprises the individual inductances of the bond wire 238, the internalportion 234, and the external portion 232 of electrical lead 230 a, andfurther including mutual inductances generated between the electricallead 230 a and the adjacent electrical lead 230 b, as well as betweenthe electrical lead 230 a and other components of the TSOP 200. Thecapacitance 903 a comprises the individual capacitances of the bond wire238, the internal portion 234, and the external portion 232 ofelectrical lead 230 a, and further including mutual capacitancesgenerated between the electrical lead 230 a and the adjacent electricallead 230 b, as well as between the electrical lead 230 a and othercomponents of the TSOP 200. The mutual inductances and mutualcapacitances are, at least in part, dependent upon the configuration of,and the distance between, the adjacent electrical leads 230 a, 230 b andupon the magnitude and frequency of the electrical signals propagatingthrough each of the adjacent electrical leads 230 a, 230 b, as well asthrough other surrounding electrical leads 230 and other components ofthe TSOP 200.

Similarly, the resistance 901 b comprises the individual resistances ofthe bond wire 238, the internal portion 234, and the external portion232 of electrical lead 230 b. The inductance 902 b comprises theindividual inductances of the bond wire 238, the internal portion 234,and the external portion 232 of electrical lead 230 b, and furtherincluding mutual inductances generated between the electrical lead 230 band the adjacent electrical lead 230 a, as well as between theelectrical lead 230 b and other components of the TSOP 200. Thecapacitance 903 b comprises the individual capacitances of the bond wire238, the internal portion 234, and the external portion 232 ofelectrical lead 230 b, and further including mutual capacitancesgenerated between the electrical lead 230 b and the adjacent electricallead 230 a, as well as between the electrical lead 230 b and othercomponents of the TSOP 200. Again, the mutual inductances and mutualcapacitances are, at least in part, dependent upon the configuration of,and the distance between, the adjacent electrical leads 230 b, 230 a andupon the magnitude and frequency of the electrical signals propagatingthrough each of the adjacent electrical leads 230 b, 230 a, as well asthrough other surrounding electrical leads 230 and other components ofthe TSOP 200.

Mutual coupling between the electrical leads of an integrated circuitpackage, and between an electrical lead and other components of theintegrated circuit package, are often difficult for the integratedcircuit package designer to accurately model, either by directcomputation methods or by using computer-based simulation techniques.However, integrated circuit package characterization is a critical, ifnot essential, aspect of the integrated circuit package design process.Package designers must be able to verify that a proposed packageconfiguration will behave electrically as intended, and that parasiticcapacitances and inductances will not compromise signal integrity. Thus,in addition to modeling the electrical behavior of an integrated circuitpackage design using direct computation methods or computer-basedsimulation, it is often desirable to directly measure certain electricalcharacteristics—such as parasitic capacitance and inductance—of anintegrated circuit package design using measuring instruments in orderto validate the electrical model.

One type of conventional measuring instrument routinely used to measureinductance and capacitance is what is often referred to as an RLC meter.There are numerous types of RLC meters commercially available from anumber of manufacturers; however, most conventional RLC meters sufferfrom the same limitation—i.e., the inability to accurately measureinductance and capacitance at high frequencies. Conventional RLC metershave an upper frequency limit of approximately 13 MHz. As noted above,new integrated circuit packages are being designed to operate infrequency ranges of 100 MHz to 400 MHz and higher, requiring thatpackage characterization be performed at frequencies up to 3 GHz andhigher in order to obtain accurate data. Thus, for newer integratedcircuit packages designed to operate at relatively high frequencies,conventional RLC meters will not provide an accurate indication of thepotential for mutual coupling in an integrated circuit package duringoperation.

One type of measuring instrument that has demonstrated an ability toprovide relatively accurate measurements of parasitic capacitances andinductances in integrated circuit packages is a vector network analyzer(VNA), which may simply be referred to as a network analyzer. Generally,a network analyzer is a two-port measuring device having the ability tosend a test signal or signals to a device under test (DUT) from one portand to receive a reflected signal or signals from the DUT at the sameport. The ratio of the reflected signal to the original test signal (ora ratio of the average of the reflected signals to the original testsignal if multiple test signals are sent) may be used to calculate whatis commonly referred to as the S₁₁ parameter or the S₂₂ parameter. Useof a network analyzer to measure a reflected signal or signals is oftenreferred to as using the network analyzer in the “S₁₁ mode.”Alternatively, the network analyzer may send a test signal or signals toa DUT from one port and receive a signal or signals transmitted throughthe DUT at the other port. The ratio of the transmitted signal to theoriginal test signal (or a ratio of the average of the transmittedsignals to the original test signal if multiple test signals are sent)may be used to calculate what is commonly referred to as the S₁₂parameter or the S₂₁ parameter. Use of a network analyzer to measure thetransmitted signal or signals is often referred to as using the networkanalyzer in the “S₁₂ mode.” Each port of the network analyzer is adaptedto both send and receive high frequency electrical signals in the 3 GHzrange as well as higher frequencies. The S₁₁, S₁₂, S₂₁, and S₂₂parameters are often referred to as “scatter” parameters.

Although traditionally used by radio frequency and transmission linedesigners, a network analyzer may be used to characterize integratedcircuit packages. In the S₁₁ mode, a network analyzer can be configuredto send a high frequency test signal or signals to a selected lead orleads of an integrated circuit package and to measure the signal orsignals reflected back from the integrated circuit package. Contactbetween a port of the network analyzer and a lead or leads of theintegrated circuit package can be established by a test probe, such as acoaxial probe, electrically connected to the port of the networkanalyzer. The power exhibited by the reflected signal (or the averagepower of multiple reflected signals if more than one test signal issent) received from the integrated circuit package is directly relatedto the impedance of the integrated circuit package and to the impedanceof the network analyzer and test probe. By appropriate test setup andcalibration, the impedance of the network analyzer and test probe can beremoved from the measured data, such that the impedance indicated by thenetwork analyzer is substantially that of the integrated circuitpackage. Also, the network analyzer may be configured to providecapacitance and inductance data for the integrated circuit package in aSmith chart format (see FIGS. 16 and 17).

Thus, a network analyzer may be used to measure the parasiticcapacitances and inductances at high frequencies of one or moreelectrical leads of an integrated circuit package. However, though it isknown in the art to use network analyzers to measure high frequencyparasitics in an integrated circuit package, conventional apparatus andmethods for acquiring such data utilize complex and expensive testfixtures and methods. For the integrated circuit package designer, whomay need an indication of the potential for mutual coupling in aproposed package design at an intermediate phase of the design process,a relatively simple, fast, and low-cost method for measuring parasiticcapacitances and inductances is preferred.

Therefore, a need exists in the art for apparatus and methods fordetermining the susceptibility of a proposed integrated circuit packagedesign to mutual coupling between electrical leads, or between anelectrical lead and other components of the integrated circuit devicepackage, using a network analyzer. Such apparatus and methods mustprovide a relatively simple and low-cost approach to integrated circuitpackage characterization.

SUMMARY OF THE INVENTION

The present invention provides apparatus and methods for measuringparasitic capacitances and inductances in integrated circuit packagesusing a network analyzer in conjunction with a coaxial probe. Accordingto the invention, simple and low-cost test fixturing and methods oftesting may be used to measure the parasitic capacitance and inductanceof one or more I/O leads of an integrated circuit package to provide apackage designer with an indication of the susceptibility of theintegrated circuit package, or a proposed package design, to mutualcoupling between electrical leads or between an electrical lead andother components of the integrated circuit package. Further, parasiticsof an integrated circuit package may be measured according to theinvention to validate an electrical model used by the package designerto model such electrical phenomena.

A method of measuring the parasitic capacitance of an I/O lead of aconventional BGA package comprises configuring all of the electricalleads of the BGA package as electrically open and contacting a signalconductor of a coaxial probe to the I/O lead of interest and contactinga ground conductor of the coaxial probe to an adjacent electrical lead,forcing the adjacent electrical lead to ground potential. Test signal orsignals—of, optionally, sweeping frequency—are provided by a networkanalyzer via the signal conductor of the coaxial probe to the I/O leadof interest, and a reflected signal or signals from the BGA package aremeasured by the network analyzer. The network analyzer then indicates aparasitic capacitance of the I/O lead of interest based on the power ofthe reflected signal (or on the average power if multiple reflectedsignals are present).

In another variation, all of the ball leads in a row or column of ballleads may be electrically interconnected to provide a larger groundreference point and to facilitate contact with the ground conductor ofthe coaxial probe. In a further embodiment, a voltage is applied to asemiconductor die of the BGA package to power the die, and thereby to atleast partially simulate actual operation of the BGA package duringtesting. In yet another embodiment, the BGA package is characterizedwithout a semiconductor die.

A method of measuring the parasitic capacitance of an I/O lead of aconventional TSOP, or other integrated circuit package configurationutilizing lead frame construction, comprises securing the TSOP to anovel test substrate configured to allow the I/O leads of the TSOP to“float” with respect to the test substrate. The test substrate includesa conductive layer configured for providing a ground plane and may alsoinclude one or more isolated conductive traces for powering asemiconductor die during testing. The test substrate may be constructedfrom printed circuit board (PCB) materials according to conventional PCBfabrication techniques. At least the I/O leads of the TSOP areconfigured as electrically open and the signal conductor of the coaxialprobe is contacted against an I/O lead of interest and the groundconductor of the coaxial probe is contacted against the conductivelayer, or ground plane, of the test substrate. Test signal orsignals—of, optionally, sweeping frequency—are provided by the networkanalyzer via the signal conductor of the coaxial probe to the I/O leadof interest, and a reflected signal or signals from the TSOP aremeasured by the network analyzer. The network analyzer then indicates aparasitic capacitance of the I/O lead of interest based on the power ofthe reflected signal (or on the average power if multiple reflectedsignals are present).

In another variation, a voltage is applied to a semiconductor die of theTSOP via the isolated conductive trace or traces to power the die, andthereby to at least partially simulate actual operation of the TSOPpackage during testing. In a further embodiment, the TSOP package ischaracterized without a semiconductor die. In yet another embodiment,one or more of the electrical leads of the TSOP is contacted against anisolated pad formed in the conductive layer of the test substrate toprovide a surface upon which an external portion of an electrical leadof the TSOP can contact and be secured to.

A method of measuring the parasitic inductance of an I/O lead of theconventional BGA package comprises removing the semiconductor die fromthe BGA package or, alternatively, constructing a “dummy” package havingno die and forming a central conductive plane on a surface of asubstrate of the BGA package. At least the I/O leads of the BGA packagethat are to be characterized are electrically connected to the centralconductive plane to establish continuity between these electrical leads.The signal conductor of the coaxial probe is contacted against an I/Olead of interest and the ground conductor of the coaxial probe iscontacted against any adjacent electrical lead of the BGA package thatis also electrically connected to the central conductive plane. Testsignal or signals—of, optionally, sweeping frequency—are provided by thenetwork analyzer via the signal conductor of the coaxial probe to theI/O lead of interest, and a reflected signal or signals from the BGApackage are measured by the network analyzer. The network analyzer thenindicates a parasitic inductance of the I/O lead of interest based onthe power of the reflected signal (or on the average power if multiplereflected signals are present). In a variation of this approach, all ofthe electrical leads of the BGA package are electrically connected tothe central conductive plane.

A method of measuring the parasitic inductance of an I/O lead of theconventional TSOP comprises removing the semiconductor die from the TSOPor, alternatively, constructing a “dummy” package having no die andforming a central conductive plane on a die-attach pad of the TSOP. Atleast the I/O leads of the TSOP that are to be characterized areelectrically connected to the central conductive plane to establishcontinuity between these electrical leads. The signal conductor of thecoaxial probe is contacted against an I/O lead of interest and theground conductor of the coaxial probe is contacted against any adjacentelectrical lead of the TSOP that is also electrically connected to thecentral conductive plane. Test signal or signals—of, optionally,sweeping frequency—are provided by the network analyzer via the signalconductor of the coaxial probe to the I/O lead of interest, and areflected signal or signals from the TSOP are measured by the networkanalyzer. The network analyzer then indicates a parasitic inductance ofthe I/O lead of interest based on the power of the reflected signal (oron the average power if multiple reflected signals are present). In avariation of this approach, all of the electrical leads of the TSOP areelectrically connected to the central conductive plane.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the features and advantages of this invention can be more readilyascertained from the following detailed description of the inventionwhen read in conjunction with the accompanying drawings, in which:

FIG. 1 shows a bottom view of an exemplary embodiment of a conventionalBGA package;

FIG. 2 shows a cross-sectional view of the conventional BGA package astaken along line II—II of FIG. 1;

FIG. 3 shows a top view of an exemplary embodiment of a conventionalTSOP;

FIG. 4 shows a cross-sectional view of the conventional TSOP as takenalong line IV—IV of FIG. 3;

FIG. 5 shows an equivalent circuit of two adjacent electrical leads inthe conventional BGA package;

FIG. 6 shows an equivalent circuit of two adjacent electrical leads inthe conventional TSOP;

FIG. 7 shows a schematic diagram of an exemplary test system that may beused for integrated circuit package characterization according to theinvention;

FIG. 8 shows a coaxial probe tip in contact with a pair of ball leads ofthe conventional BGA package to measure parasitic capacitance accordingto the present invention;

FIG. 9 shows a test substrate according to the present invention for usein measuring parasitic capacitance of an electrical lead of theconventional TSOP;

FIG. 10 shows the test substrate of FIG. 9 having the conventional TSOPdisposed thereon for measuring parasitic capacitance according to thepresent invention;

FIG. 11 shows a coaxial probe tip in contact with a lead of theconventional TSOP and a surface of the test substrate of FIG. 9 tomeasure parasitic capacitance according to the present invention;

FIG. 12 shows a coaxial probe tip in contact with a lead of theconventional TSOP and a surface of another embodiment of a testsubstrate according to the present invention for measuring parasiticcapacitance;

FIG. 13 shows a portion of the conventional BGA package having a centralconductive plane according to the present invention for measuringparasitic inductance;

FIG. 14 shows a portion of the conventional BGA package having a centralconductive plane according to another embodiment of the invention formeasuring parasitic inductance;

FIG. 15 shows a portion of the conventional TSOP having a centralconductive plane according to the present invention for measuringparasitic inductance;

FIG. 16 shows parasitic capacitance data for an integrated circuitpackage presented in a Smith chart format; and

FIG. 17 shows parasitic inductance data for an integrated circuitpackage presented in a Smith chart format.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a number of embodiments of apparatus andmethods for measuring parasitic capacitances and inductances inintegrated circuit packages using a network analyzer. Although theapparatus and methods according to the invention are described inrelation to the conventional BGA package 100 and the conventional TSOP200 shown and described with respect to FIGS. 1 and 2 and FIGS. 3 and 4,respectively, it should be understood by those of ordinary skill in theart that the present invention may be applicable to the characterizationof any type of integrated circuit package.

As noted above, the present invention encompasses apparatus and methodsfor measuring both mutual capacitance and mutual inductance in anintegrated circuit package using a network analyzer. Referring to FIG.7, an exemplary embodiment of a test system 10 that may be used tomeasure parasitic capacitances and inductances of an integrated circuitpackage is shown. The test system 10 includes a network analyzer 20having a first port 21 and a second port 22. The first port 21 (or,optionally, the second port 22) of the network analyzer 20 iselectrically connected to a coaxial test probe 30. The coaxial testprobe 30 is configured to establish electrical contact with one or moreelectrical leads of a device under test (DUT) 5, such as theconventional BGA package 100 or the conventional TSOP 200, which may besupported in a test fixture 50. Also, the coaxial test probe 30 may forma part of, or be supported in, a probe station 40, the probe station 40being configured to provide accurate positioning of the coaxial testprobe 30 relative to the DUT 5. The network analyzer may be used in theS₁₁ mode (or, optionally, in the S₂₂ mode) to measure parasiticcapacitances and inductances of the electrical leads of the DUT 5.

The exemplary test system 10 may include a network analyzer 20comprising an HP 8753E Vector Network Analyzer manufactured by HewlettPackard or an 8753ES Vector Network Analyzer manufactured by AgilentTechnologies. The probe station 40 may comprise a GTL-4000 SeriesPrecision Large-Area Probing System manufactured by GigaTest Labs.Further, the exemplary test system 10 may include a coaxial test probe30 comprising a Picoprobe® Model 40A Microwave Probe manufactured by GGBIndustries.

The exemplary test system 10 may be used, in conjunction with novel testfixturing and test methods according to the invention, to determine thepotential for mutual coupling in an integrated circuit package, as willnow be described in greater detail.

The present invention encompasses apparatus and methods for measuringparasitic capacitance in an integrated circuit package and apparatus andmethods for measuring parasitic inductance in an integrated circuitpackage. The parasitic capacitance and inductance measurements areindicative of the susceptibility of an integrated circuit package tomutual coupling between electrical leads or between an electrical leadand other components of the integrated circuit package, which maycompromise signal integrity, as noted above. The apparatus and methodsof the present invention are described herein in the context ofmeasuring parasitic capacitance in the conventional BGA package 100,measuring parasitic capacitance in the conventional TSOP 200, measuringparasitic inductance in the conventional BGA package 100, and measuringparasitic inductance in the conventional TSOP 200. However, it should beunderstood by those of ordinary skill in the art that the embodimentsdisclosed herein of apparatus and methods for measuring parasiticcapacitances and inductances are applicable to the characterization ofany type of integrated circuit package configuration known in the art,as noted above.

To measure the parasitic capacitance of an I/O lead 130 on theconventional BGA package 100, the BGA package 100 is mounted with theball leads 132 facing upwards, as shown in FIG. 8. A coaxial test probe30 is electrically connected to the first port 21 (or, optionally, thesecond port 22) of a network analyzer 20. The network analyzer 20 andcoaxial test probe 30 are calibrated to the tip of the coaxial testprobe 30. In other words, parasitic capacitances of the network analyzer20 and coaxial test probe 30 will be removed from the measured data. Thenetwork analyzer 20 is then configured to operate in the S₁₁ mode (or,optionally, the S₂₂ mode), such that an electrical test signal orsignals are sent from the first port 21 of the network analyzer 20 and areflected signal or signals are received at the first port 21.

All of the electrical leads 130 of the conventional BGA package 100 mustbe configured as electrically open—i.e., no electrical lead 130 iselectrically shorted to another electrical lead 130. Alternatively, theelectrical leads 130 of the BGA package 100 may be configured to exhibita high input impedance, such that the impedance between any two adjacentelectrical leads 130 is sufficient to electrically isolate eachelectrical lead 130 from all adjacent electrical leads 130, eachelectrical lead 130 thereby being essentially electrically open.

Referring to FIG. 8, the coaxial test probe 30 is then contacted againstthe ball lead 132 a of an electrical lead 130 a that is to becharacterized and an adjacent ball lead 132 b of another electrical lead130 b. The tip of the coaxial test probe 30 comprises a signal conductor31 and a ground conductor 32. The signal conductor 31 is contactedagainst the ball lead 132 a of the I/O lead 130 a to be characterized toestablish electrical communication therebetween. Similarly, the groundconductor 32 is contacted against the adjacent ball lead 132 b of theelectrical lead 130 b to establish electrical contact therebetween. Theground conductor 32 of the coaxial test probe 30 provides a groundpotential and forces the electrical lead 130 b to the ground potential.

To measure the parasitic capacitance of the I/O lead 130 a, a testsignal or signals are sent via the signal conductor 31 of the coaxialtest probe 30 to the I/O lead 130 a. A signal or signals reflected fromthe BGA package 100 through the I/O lead 130 a will then be received bythe coaxial test probe 30 and provided to the network analyzer 20. Asnoted above, the reflected signal or signals from the BGA package 100can be directly related to the impedance of the I/O lead 130 a. Thenetwork analyzer 20 is configured to equate the reflected signal orsignals to an impedance measurement such that the parasitic capacitancecan be determined. All of the I/O leads 130 of the BGA package 100, or aselected portion thereof, may be characterized in a similar manner.

The test signal or signals provided by the network analyzer 20 via thesignal conductor 31 of the coaxial test probe 30 may comprise afrequency sweep in which signals increasing in frequency between aselected start frequency and a selected end frequency are provided tothe I/O lead 130 a. The network analyzer may, therefore, provide anindication of the parasitic capacitance at various frequencies betweenthe start and end frequencies. A typical frequency sweep may comprise,for example, a 401 point sweep providing data at 401 discrete frequencypoints between, and including, the start and end frequencies.

For the conventional BGA package 100 shown and described herein, theelectrical leads 130 in the outer column 151 (as well as in inner column153) are I/O leads and the electrical leads in the adjacent middlecolumn 152 are either a V_(CC), V_(SS), or V_(REF) lead. Thus, theelectrical lead 130 b having adjacent ball lead 132 b comprises a V_(CC)lead, a V_(SS) lead, or a V_(REF) lead and, again, the ground conductor32 of the coaxial test probe 30 forces this V_(CC), V_(SS), or V_(REF)lead to ground potential during testing. Although, for the conventionalBGA package 100, each I/O lead 130 in the outer and inner columns 151,161, 153, 163 will have a ball lead 132 that is adjacent to another balllead 132 of a V_(CC), V_(SS), or V_(REF) lead 130 in the middle column152, 162, an I/O lead 130 may be characterized by contacting the signalconductor 31 of the coaxial test probe 30 to that I/O lead andcontacting the ground conductor 32 of the coaxial test probe 30 to anadjacent ball lead 132 of another I/O lead 130, which is then forced toground potential. Thus, the parasitic capacitance of an I/O lead 130 maybe measured between that I/O lead and any adjacent lead 130, so long asthe adjacent lead is forced to ground potential by contact with theground conductor 32 of the coaxial test probe 30. Further, it should benoted that, for accurate measurements to be obtained, ground potentialshould be provided by only the network analyzer 20.

In an alternative embodiment, all of the electrical leads 130 in themiddle column 152 (and/or middle column 162) may be electricallyinterconnected by, for example, a wire or bus bar 170, as shown in FIG.1. The wire or bus bar 170 may be attached to the ball leads 132 in themiddle column 152 using solder or conductive epoxy or, alternatively,may be secured against all of the ball leads 132 in the middle column152 by a clamping device or other fixture (not shown). Theinterconnected electrical leads 130 of the middle column 152 provide alarger ground reference point and may facilitate contact with the groundconductor 32 of the coaxial test probe 30.

In a further embodiment, a voltage is applied to one or more of theV_(CC) leads on the conventional BGA package 100 to power thesemiconductor die 110 during testing. During operation of the BGApackage 100, functioning of the semiconductor die 110 may itselfintroduce or effect the parasitic capacitances and inductances in theI/O leads 130 electrically connected thereto. Powering the semiconductordie 110 of the BGA package 100 during testing may, therefore, provide anindication of the mutual coupling that may occur within the BGA package100 during actual operation.

In yet another embodiment, the semiconductor die 110 of the conventionalBGA package 100 may be removed (or a “dummy” BGA package constructedwithout a semiconductor die 110) for testing. In this embodiment, onlythe electrical leads 130 and substrate 105 are characterized during atest sequence.

To measure the parasitic capacitance of an electrical lead 230 of theconventional TSOP 200, the TSOP 200 is secured to a test substrateconfigured to allow the I/O leads 230 of the conventional TSOP 200 to“float.” Referring to FIGS. 9, 10, and 11, the test substrate 300comprises an insulative base layer 310 and a conductive layer 320 formedon a surface of the insulative base layer 310. The insulative base layer310 may be comprised of any suitable dielectric or electricallyinsulating material, and the conductive layer 320 may comprise anysuitable conductive material known in the art. By way of example, thetest substrate 300 may simply comprise a printed circuit board (PCB)material, such as FR-4 or other fiberglass materials, having a layer ofcopper formed on a surface thereof. Such a test substrate 300 may beformed using conventional PCB fabrication techniques. At locations 301on the test substrate 300 corresponding to locations of the externalportion 232 of the I/O leads 230 of the TSOP 200 to be secured thereon,a cavity 322 is formed through at least the conductive layer 320 toexpose the insulative base layer 310 lying underneath. The cavity 322may also extend a depth into the insulative base layer 310.

One or more isolated conductive traces 324 may also be formed in theconductive layer 320 of the test substrate 300. The conductive trace ortraces 324 each comprise a trunk line 325 having one or more branchlines 326 extending therefrom, each branch line 326 terminating at alocation 302 corresponding to a location of the external portion 232 ofa V_(CC) lead 230 of the TSOP 200 to be secured to the test substrate300. The isolated conductive traces 324 provide an electrical path tothe semiconductor die 210 of the conventional TSOP 200 for powering thesemiconductor die 210 during testing.

At locations 303 on the test substrate 300 corresponding to locations ofthe V_(SS) and V_(REF) leads 230 of the TSOP 200 to be secured thereon,the conductive layer 320 has not been removed. The conductive layer 320,therefore, provides a ground plane to which the V_(SS) and V_(REF) leads230 of the conventional TSOP 200 can be electrically connected fortesting.

Referring to FIGS. 10 and 11, to measure the parasitic capacitance of anelectrical lead 230 of the TSOP 200, the TSOP is secured to the testsubstrate 300 such that all I/O leads 230 of the TSOP 200 are eachdisposed at one of the locations 301 on the test substrate 300 and issuspended over one of the cavities 322 formed in the conductive layer320. Thus, the external portion 232 of each electrical lead 230 does notmake contact with any surface of the test substrate 300, as shown inFIG. 11. All of the V_(CC) leads 230 of the TSOP 200 are each disposedat one of the locations 302 on the test substrate 300 and areelectrically connected to one of the branch lines 326 of the isolatedconductive traces 324. Further, all of the V_(SS) and V_(REF) leads 230of the TSOP 200 are each disposed at one of the locations 303 on thetest substrate 300 and are electrically connected to the conductivelayer 320. The TSOP 200 may be secured to the test substrate 300 byattaching the external portion 232 of each V_(CC), V_(SS), and V_(REF)lead 230 to the test substrate 300 using solder or, alternatively, theTSOP 200 may be secured to the test substrate 300 with any type ofclamping device (not shown).

A coaxial test probe 30 is electrically connected to the first port 21(or, optionally, the second port 22) of a network analyzer 20. Thenetwork analyzer 20 and coaxial test probe 30 are calibrated to the tipof the coaxial test probe 30. In other words, parasitic capacitances ofthe network analyzer 20 and coaxial test probe 30 will be removed fromthe measured data, as noted above. The network analyzer 20 is thenconfigured to operate in the S₁₁ mode (or, optionally, the S₂₂ mode),such that electrical test signal or signals are sent from the first port21 of the network analyzer 20 and the reflected signal or signals arereceived at the first port 21.

All of the electrical leads 230 of the conventional TSOP 200 must beconfigured as electrically open—i.e., no electrical lead 230 iselectrically shorted to another electrical lead 230 (other than theV_(SS) and V_(REF) leads which are coupled to the conductive layer 320of the test substrate 300). Alternatively, the electrical leads 230 ofthe TSOP 200 may be configured to exhibit a high input impedance, suchthat the impedance between any two adjacent electrical leads 230 issufficient to electrically isolate each electrical lead 230 from alladjacent electrical leads 230. Each electrical lead 230 is, therefore,essentially electrically open.

Referring to FIG. 11, the coaxial test probe 30 is then contactedagainst the external portion 232—which, again, is free-floating withrespect to the test substrate 300—of an electrical lead 230 that is tobe characterized and the conductive layer 320 on the test substrate 300.The signal conductor 31 is contacted against the external portion 232 ofthe electrical lead 230 to be characterized to establish electricalcommunication therebetween. Similarly, the ground conductor 32 iscontacted against the conductive layer 320 to establish electricalcontact therebetween. The ground conductor 32 of the coaxial test probe30 forces the conductive layer 320 to the ground potential and, as notedabove, in order to obtain accurate data, ground potential should beprovided by only the network analyzer 20.

To measure the parasitic capacitance of the electrical lead 230, a testsignal or signals are sent via the signal conductor 31 of the coaxialtest probe 30 to the electrical lead 230. The signal or signalsreflected from the TSOP 200 through the electrical lead 230 will then bereceived by the coaxial test probe 30 and provided to the networkanalyzer 20. The reflected signal or signals from the TSOP 200 can bedirectly related to the impedance of the electrical lead 230. Thenetwork analyzer 20 is configured to equate the reflected signal orsignals to an impedance measurement such that the parasitic capacitancecan be determined. Because the external portion 232 of the electricallead 230 being characterized is free-floating with respect to the testsubstrate 300 (i.e., not contacting any surface of the test substrate300), any parasitic capacitance present in the test substrate 300 willnot be measured by the network analyzer 20. The parasitic capacitance ofall of the I/O leads 230 of the TSOP 200, or a selected portion thereof,may similarly be measured.

As noted above, the test signal or signals provided by the networkanalyzer 20 via the signal conductor 31 of the coaxial test probe 30 maycomprise a frequency sweep in which signals increasing in frequencybetween a selected start frequency and a selected end frequency areprovided to the electrical lead 230, thereby providing an indication ofthe parasitic capacitance at various frequencies at and between thestart and end frequencies.

In an alternative embodiment, a voltage is applied to one or more of theV_(CC) leads on the conventional TSOP 200 to power the semiconductor die210 during testing. The voltage potential is applied to the V_(CC) leadsvia the isolated conductive traces 324 (each comprising trunk line 325and branch line or lines 326). During operation of the TSOP 200,functioning of the semiconductor die 210 may itself introduce or effectthe parasitic capacitances and inductances in the I/O leads 230electrically connected thereto. Accordingly, powering the semiconductordie 210 of the TSOP 200 during testing may provide an indication of themutual coupling that may occur within the TSOP 200 during actualoperation. If it is not desired to power the semiconductor die 210during testing, the isolated conductive traces 324 may be electricallyconnected to the conductive layer 320 to force the V_(CC) leads toground potential upon contact between the ground conductor 32 of thecoaxial test probe 30 and the conductive layer 320.

In a further embodiment, the semiconductor die 210 of the conventionalTSOP 200 may be removed for testing (or a “dummy” TSOP constructedwithout a semiconductor die 210). In this embodiment, only theelectrical leads 230 (as well as other portions of a lead frame) arecharacterized during a test sequence. With the semiconductor die 210removed, the isolated conductive traces 324 may be electricallyconnected to the conductive layer 320, such that the V_(CC) leads arealso forced to ground potential by contact of the ground conductor 32 ofthe coaxial test probe 30 with the conductive layer 320.

In yet another embodiment, as shown in FIG. 12, an isolated pad 328 isformed in the conductive layer 320 of the test substrate 300 at each ofthe locations 301 corresponding to the locations of the external portion232 of the I/O leads 230 of the TSOP 200 to be secured on the testsubstrate 300 for characterization. The isolated pads 328 provide asurface upon which the external portion 232 of each electrical lead 230of the TSOP 200 can rest and, if desired, be attached to. However, theisolated pads 328 electrically isolate each electrical lead 230 from theconductive layer 320, which is forced to ground potential duringtesting. In this embodiment, because the I/O leads 230 are in contactwith the test substrate 300, the test substrate 300 must becharacterized prior to testing of an integrated circuit package, suchthat the parasitic capacitance of each isolated pad 328 is known and canbe subtracted from the measured parasitic capacitance for an electricallead 230 in contact therewith. Characterization of the I/O leads 230 ofthe TSOP 200 then proceeds as described above.

Referring to FIG. 16, exemplary data for the parasitic capacitance of anI/O lead of an integrated circuit package is shown. The data ispresented in a Smith chart 1000 format, which may be provided directlyby the network analyzer 20. The Smith chart 1000 includes mutuallyorthogonal lines of constant resistance 1010 and lines of constantreactance 1020, which may be either capacitive or inductive. Theoutermost line of constant resistance 1010 a corresponds to a resistanceof zero. In the portion 1040 above the central axis 1030 of the Smithchart 1000 the reactance is inductive, and in the portion 1050 below thecentral axis 1030 the reactance is capacitive. A generally smooth curve1060 depicts the parasitic capacitance for an I/O lead of an integratedcircuit package measured according to the present invention. The smoothcurve 1060 represents a best-fit curve connecting a selected number ofindividual parasitic capacitance data points measured at a selected,discrete frequencies.

To measure the parasitic inductance of an I/O lead 130 of theconventional BGA package 100, the semiconductor die 110 is removed fromthe BGA package 100 (or a “dummy” BGA package is constructed without asemiconductor die 110) and all of the electrical leads 130 of the BGApackage are electrically connected to a central conductive plane.Referring to FIG. 13, the central conductive plane 150 a may be formeddirectly on the substrate 105 at a location substantially correspondingto a location of the die-attach pad 112 (which has been removed or,alternatively, a “dummy” BGA package is constructed without thedie-attach pad 112). Bond wires 138 may be used to electrically connectthe bond end 137 of each electrical lead 130 to the central conductiveplane 150 a. In another embodiment, as shown in FIG. 14, the centralconductive plane 150 b is formed on the die-attach pad 112 and a bondwire 138 may be used to electrically connect the bond end 137 of eachelectrical lead 130 to the central conductive plane 150 b. In a furtherembodiment, an encapsulant material 120 may be formed over the uppersurface 106 of the substrate 105 to encapsulate at least a portion ofeach electrical lead 130 and the central conductive plane 150 a, 150 b,as shown in FIGS. 13 and 14.

The central conductive plane 150 a, 150 b may be constructed of anysuitable conductive material and according to any suitable methods knownin the art. For example, the central conductive plane 150 a, 150 b may,for example, comprise an alumina substrate formed on the substrate 105or die-attach pad 112 or a layer of conductive epoxy adhered to thesubstrate 105 or die-attach pad 112. Although shown in FIGS. 13 and 14as a generally planar structure, the central conductive plane 150 a, 150b may be of any suitable shape or configuration, so long as the centralconductive plane 150 a, 150 b provides a point at which continuity maybe established between the electrical leads 130 of the BGA package 100.

A coaxial test probe 30 is electrically connected to the first port 21(or, optionally, the second port 22) of a network analyzer 20. Thenetwork analyzer 20 and coaxial test probe 30 are calibrated to the tipof the coaxial test probe 30, such that the parasitic inductances of thenetwork analyzer 20 and coaxial test probe 30 are removed from themeasured data. The network analyzer 20 is then configured to operate inthe S₁₁ mode (or, optionally, the S₂₂ mode), such that electrical testsignal or signals are sent from the first port 21 of the networkanalyzer 20 and the reflected signal or signals are received at thefirst port 21.

Referring again to FIG. 8, the coaxial test probe 30 is then contactedagainst the ball lead 132 a of an I/O lead 130 a that is to becharacterized and an adjacent ball lead 132 b of another electrical lead130 b. The signal conductor 31 is contacted against the ball lead 132 aof the I/O lead 130 a to be characterized to establish electricalcommunication therebetween and, similarly, the ground conductor 32 iscontacted against the adjacent ball lead 132 b of the electrical lead130 b to establish electrical contact therebetween. A circuit is thusformed between the ball lead 132 a and the ball lead 132 b having aninductance therebetween comprising the individual parasitic inductanceof the I/O lead 130 a to be characterized and the individual parasiticinductance of the other electrical lead 130 b, which are in series.

To measure the parasitic inductance of the I/O lead 130 a, a test signalor signals are sent via the signal conductor 31 of the coaxial testprobe 30 to the I/O lead 130 a. A signal or signals reflected from theBGA package 100 through the I/O lead 130 a will then be received by thecoaxial test probe 30 and provided to the network analyzer 20. Thereflected signal or signals from the BGA package 100 can be directlyrelated to the impedance of the I/O lead 130 a. The network analyzer 20is configured to equate the reflected signal or signals to an impedancemeasurement such that the parasitic inductance can be determined.However, because the parasitic inductance of the electrical lead 130 bis being added in series to the parasitic inductance of the I/O lead 130a being characterized, the measured parasitic inductance is divided bytwo to obtain the individual parasitic inductance of the I/O lead 130 a.This result assumes, of course, that the parasitic inductances of thetwo adjacent electrical leads 130 a, 130 b are approximately equal. Thisassumption will introduce some error into the measured data due todifferences in length, thickness, and width of the adjacent electricalleads 130 a, 130 b; however, it is believed that, for the purpose ofpackage characterization during the design process, such errors will notbe significant. All of the I/O leads 130 of the BGA package 100, or aselected portion thereof, may be characterized in a similar manner.

The test signal or signals provided by the network analyzer 20 via thesignal conductor 31 of the coaxial test probe 30 may comprise afrequency sweep in which signals increasing in frequency between aselected start frequency and a selected end frequency are provided tothe electrical lead 130 a. The network analyzer may, therefore, providean indication of the parasitic inductance at various frequencies betweenthe start and end frequencies. A typical frequency sweep may comprise,for example, a 401 point sweep providing data at 401 discrete frequencypoints between, and including, the start and end frequencies.

It is not necessary that every electrical lead 130 of the conventionalBGA package 100 be electrically connected to the central conductiveplane 150 a, 150 b, so long as all of the I/O leads 130 to becharacterized are electrically connected thereto. For example, theV_(CC), V_(SS), or V_(REF) leads would not need to be electricallyconnected to the central conductive plane 150 a, 150 b. Further, theparasitic inductance of an I/O lead 130 may be measured directly betweenthe ball lead 132 of that I/O lead 130 and the central conductive plane150 a, 150 b by electrically connecting the ground conductor 32 of thecoaxial test probe 30 to the central conductive plane 150 a, 150 b, inwhich case the parasitic inductance of only that I/O lead 130 ismeasured. However, electrically connecting the ground conductor 32 ofthe coaxial test probe 30 to the central conductive plane 150 a, 150 bmay require either a large pitch (i.e., the distance between the signaland ground conductors 31, 32) coaxial test probe 30 or a wire or otherconductor extending between the ground conductor 32 and the centralconductive plane 150 a, 150 b. A large pitch probe or a conductorextending from the ground conductor 32 of the coaxial test probe 30 tothe central conductive plane 150 a, 150 b may each itself exhibit aparasitic inductance that could effect the measured parasitic inductanceof an I/O lead 130.

Therefore, as a matter of convenience, all of the electrical leads 130of the conventional BGA package 100 may be electrically connected to thecentral conductive plane 150 a, 150 b, such that every I/O lead 130 tobe characterized will have a ball lead 132 lying adjacent to a ball lead132 of another electrical lead 130 electrically connected to the centralconductive plane 150 a, 150 b, thereby enabling the smallest possiblepitch coaxial test probe 30 (i.e., one having a pitch substantially thesame as the distance between any two ball leads 132) to be used andeliminating the need to extend a conductor from the ground conductor 32of the coaxial test probe 30 to the central conductive plane 150 a, 150b.

To measure the parasitic inductance of an electrical lead 230 of theconventional TSOP 200, the semiconductor die 210 is removed from theTSOP 200 (or a “dummy” TSOP is constructed without a semiconductor die210) and all of the electrical leads 230 of the TSOP 200 areelectrically connected to a central conductive plane. Referring to FIG.15, the central conductive plane 251 may, for example, be formeddirectly on the die-attach pad 212. A bond wire 138 may be usedelectrically to connect the bond end 235 of each electrical lead 230 tothe central conductive plane 251. One or more bond wires 238 may alsoelectrically connect the bus bar or bars 239 to the central conductiveplane 251. In another embodiment, an encapsulant material 220 mayencapsulate the central conductive plane 251 and at least a portion ofeach electrical lead 130, as shown in FIG. 15.

The central conductive plane 251 may be constructed of any suitableconductive material and according to any suitable methods known in theart. For example, the central conductive plane 251 may, for example,comprise an alumina substrate formed on the die-attach pad 212 or alayer of conductive epoxy adhered to the die-attach pad 212. Althoughshown in FIG. 15 as a generally planar structure, the central conductiveplane 251 may be of any suitable shape or configuration, so long as thecentral conductive plane 251 provides a point at which continuity may beestablished between the electrical leads 230 of the TSOP 200.

A coaxial test probe 30 is electrically connected to the first port 21(or, optionally, the second port 22) of a network analyzer 20. Thenetwork analyzer 20 and coaxial test probe 30 are calibrated to the tipof the coaxial test probe 30, such that the parasitic inductances of thenetwork analyzer 20 and coaxial test probe 30 are removed from themeasured data, as noted above. The network analyzer 20 is thenconfigured to operate in the S₁₁ mode (or, optionally, the S₂₂ mode),such that electrical test signal or signals are sent from the first port21 of the network analyzer 20 and the reflected signal or signals arereceived at the first port 21, also as noted above.

The coaxial test probe 30 is then contacted against the external portion232 of the electrical lead 230 to be characterized and the externalportion 232 of another adjacent electrical lead 230 that is electricallyconnected to the central conductive plane 251. The signal conductor 31is contacted against the external portion 232 of the electrical lead 230to be characterized to establish electrical communication therebetweenand, similarly, the ground conductor 32 is contacted against theexternal portion 232 of the adjacent electrical lead 230 to establishelectrical contact therebetween. A circuit is thus formed between theexternal portion 232 of the electrical lead 230 being characterized andthe external portion 232 of the other adjacent electrical lead 230having an inductance therebetween comprising the individual parasiticinductance of the electrical lead 230 to be characterized and theindividual parasitic inductance of the other adjacent electrical lead230, which are in series.

To measure the parasitic inductance of the electrical lead 230 beingcharacterized, a test signal or signals are sent via the signalconductor 31 of the coaxial test probe 30 to that electrical lead 230.The signal or signals reflected from the TSOP 200 through the electricallead 230 being characterized will then be received by the coaxial testprobe 30 and provided to the network analyzer 20. As noted above, thereflected signal or signals from the TSOP 200 can be directly related tothe impedance of the electrical lead 230 being characterized. Thenetwork analyzer 20 is configured to equate the reflected signal orsignals to an impedance measurement such that the parasitic inductancecan be determined. However, because the parasitic inductance of theelectrical lead 230 being characterized is added in series to theparasitic inductance of the other adjacent electrical lead 230, themeasured parasitic inductance is divided by two to obtain the individualparasitic inductance of the electrical lead 230 being characterized.This result assumes, of course, that the parasitic inductances of theelectrical lead 230 being characterized and the other adjacentelectrical lead 230 are approximately equal. This assumption willintroduce some error into the measured data due to differences inlength, thickness, and width of the electrical lead 230 beingcharacterized and any adjacent electrical leads 230; however, it isbelieved that, for the purpose of package characterization during thedesign process, such errors will not be significant, as was noted above.All of the I/O leads 230 of the TSOP 200, or a selected portion thereof,may be characterized in a similar manner.

The test signal or signals provided by the network analyzer 20 via thesignal conductor 31 of the coaxial test probe 30 may comprise afrequency sweep in which signals increasing in frequency between aselected start frequency and a selected end frequency are provided tothe electrical lead 230 being characterized. The network analyzer may,therefore, provide an indication of the parasitic inductance at variousfrequencies between the start and end frequencies, as noted above.

It is not necessary that every electrical lead 230 of the conventionalTSOP 200 be electrically connected to the central conductive plane 251,so long as all of the I/O leads 230 to be characterized are electricallyconnected thereto. For example, the V_(CC), V_(SS), or V_(REF) leadswould not need to be electrically connected to the central conductiveplane 251. Further, the parasitic inductance of an electrical lead 230may be measured directly between the external portion 232 of thatelectrical lead 230 and the central conductive plane 251 by electricallyconnecting the ground conductor 32 of the coaxial test probe 30 to thecentral conductive plane 251, in which case the parasitic inductance ofonly that electrical lead 230 is measured. However, electricallyconnecting the ground conductor 32 of the coaxial test probe 30 to thecentral conductive plane 251 may require either a large pitch coaxialtest probe 30 or a wire or other conductor extending between the groundconductor 32 and the central conductive plane 251. A large pitch probeor a conductor extending from the ground conductor 32 of the coaxialtest probe 30 to the central conductive plane 251 may each itselfexhibit a parasitic inductance that could effect the measured parasiticinductance of an electrical lead 230.

Therefore, as a matter of convenience, all of the electrical leads 230of the conventional TSOP 200 may be electrically connected to thecentral conductive plane 251, such that every electrical lead 230 to becharacterized will have an external portion 232 lying adjacent to theexternal portion 232 of another electrical lead 230 that is electricallyconnected to the central conductive plane 251, thereby enabling thesmallest possible pitch coaxial test probe 30 (i.e., one having a pitchsubstantially the same as the distance between any two external portions232 of two adjacent electrical leads 230) to be used and eliminating theneed to extend a conductor from the ground conductor 32 of the coaxialtest probe 30 to the central conductive plane 251.

Referring to FIG. 17, exemplary data for the parasitic inductance of anI/O lead of an integrated circuit package is shown. The data ispresented in a Smith chart 1100 format, which may be provided directlyby the network analyzer 20, as noted above. The Smith chart 1100includes mutually orthogonal lines of constant resistance 1110 and linesof constant reactance 1120, which may be either capacitive or inductive.The outermost line of constant resistance 1110 a corresponds to aresistance of zero. In the portion 1140 above the central axis 1130 ofthe Smith chart 1100 the reactance is inductive, and in the portion 1150below the central axis 1130 the reactance is capacitive. A generallysmooth curve 1160 depicts the parasitic inductance for an I/O lead of anintegrated circuit package measured according to the present invention.The smooth curve 1160 represents a best-fit curve connecting a selectednumber of individual parasitic inductance data points measured atselected, discrete frequencies.

For measuring parasitic capacitance and for measuring parasiticinductance according to the invention, irrespective of the integratedcircuit package configuration, electrical signal or signals are providedto the I/O lead being characterized (and, for inductance measurements,to one adjacent electrical lead) by a network analyzer 20 via the signalconductor 31 of a coaxial test probe 30. However, during actualoperation of an integrated circuit package, such as the conventional BGApackage 100 or the conventional TSOP 200, all of the electrical leads inproximity to the I/O lead of interest, as well as the semiconductor die110, may have electrical signals propagating therethrough. Although theapparatus and methods of the present invention may not simulate such anoperational environment, it is believed that the parasitic capacitanceand inductance measured according to the invention for any individualI/O lead provide an indication of the potential for mutual coupling ofthat I/O lead with other adjacent electrical leads and other componentsof the integrated circuit package. Thus, characterization of all of theI/O leads of an integrated circuit package using apparatus and methodsaccording to the present invention provides an indication of the signalintegrity provided by an integrated circuit package or a proposedpackage design.

Apparatus and methods for measuring mutual coupling in an integratedcircuit package according to the present invention having been hereindescribed, those of ordinary skill in the art will appreciate the manyadvantages of the present invention. The apparatus and methods of thepresent invention provide an integrated circuit package designer with asimple, low-cost, and relatively quick method of measuring the parasiticcapacitances and inductances of the I/O leads of an integrated circuitpackage using a commercially available network analyzer and coaxialprobe. The parasitic capacitances and inductances measured according tothe invention may provide a package designer with an indication of thesusceptibility of a proposed package design to mutual coupling betweenI/O leads and between and I/O lead and other components of theintegrated circuit package. Further, parasitic capacitances andinductances measured according to the invention provide the packagedesigner with a tool for validating design models.

Parasitic capacitance of an I/O lead of a conventional BGA package 100may be measured according to a simple test method with minimalfixturing, which may include connecting a wire or bus bar 170 across acolumn 152, 162 of ball leads 132. A simple test method in conjunctionwith a non-complex, low-cost test substrate 300, which may beconstructed from printed circuit board materials according to well knownPCB fabrication techniques, may be used to measure parasitic capacitanceof an I/O lead of a conventional TSOP 200 or other similar package typeshaving lead frame construction. The parasitic capacitance of anintegrated circuit package may be measured without the semiconductor die110 by removing the die from the package or, alternatively, byconstructing a “dummy” package without a die.

Parasitic inductance of an I/O lead of either a conventional BGA package100 or TSOP 200, as well as other known package configurations, may bemeasured using a simple test method with minimal test setup. Test setupmay include removing the semiconductor die from an integrated circuitpackage or, alternatively, constructing a “dummy” package having no dieand forming a central conductive plane 150 a, 150 b, 251 in theintegrated circuit package configured to provide continuity between allof the electrical leads of the package.

The foregoing detailed description and accompanying drawings are onlyillustrative and not restrictive. They have been provided primarily fora clear and comprehensive understanding of the present invention and nounnecessary limitations are to be understood therefrom. Numerousadditions, deletions, and modifications to the embodiments of thepresent invention, as well as alternative arrangements, may be devisedby those skilled in the art without departing from the spirt of thepresent invention and the scope of the appended claims.

What is claimed is:
 1. A test assembly, comprising: a test substrateincluding an insulative base layer and a conductive layer formed on atleast a portion of a surface of said insulative base layer, said testsubstrate further including at least one cavity formed in saidconductive layer to expose said insulative base layer; and an electricalcomponent having a plurality of leads extending therefrom disposed onsaid test substrate, one lead of said plurality of leads aligned withsaid at least one cavity and not contacting any surface of said testsubstrate and at least one other lead of said plurality of leadscontacting said conductive layer.
 2. The test assembly of claim 1,wherein said test substrate further comprises at least one isolatedconductive trace formed in said conductive layer located and configuredto provide an electrical signal to another lead of said plurality ofleads extending from said electrical component.